1. Field of the Invention
The present invention relates to a semiconductor storage device for performing refresh operation to hold date stored in a memory cell array. Particularly, the present invention relates to a semiconductor storage device for performing refresh operation in which connection state of bit lines is properly switched by switch means.
2. Description of the Related Art
As a general configuration of a semiconductor storage device such as DRAM, such a configuration in which a memory cell array is divided into a plurality of banks and each bank is further divided into a plurality of unit blocks has been well known. Data is stored and held in memory cells formed at intersections between a plurality of word lines and a plurality of bit lines in each unit block. In conventional DRAM, a row of sense amplifiers including a plurality of sense amplifiers is arranged on each of both sides of the unit block. A configuration in which switches are provided between the unit block and the row of sense amplifiers has been also proposed (see, for example, Japanese Patent Laid-Open No. 2004-103657).
Meanwhile, refresh operation needs to be performed at a predetermined time interval in order to hold data stored in DRAM. This refresh operation is so controlled that after bit lines of the unit block are pre-charged, a word line selected to be refreshed is activated, data of memory cells on the selected word line is read out through the bit lines, and the data is amplified by the row of sense amplifiers and is rewritten to the memory cells. Low power consumption of devices for mobile use such as DRAM is strongly required, and particularly reduction of current consumption in self refresh operation during stand-by is a problem. For its purpose, it is required to reduce current consumption of DRAM in self refresh operation and to prolong an interval of self refresh.
However, since a number of memory cells are formed on the bit lines included in each unit block, capacitance of the bit lines becomes larger, thereby increasing charge and discharge currents necessary in self refresh. Further, large sense margin of the sense amplifiers cannot be secured because of the capacitance of the bit lines increases, and a sufficiently long interval of self refresh cannot be obtained. Due to these factors, it is inevitable that current consumption in self refresh operation increases. On the other hand, in order to reduce current consumption in self refresh, the unit blocks may be formed in small size so as to reduce the capacitance of the bit lines. However, by employing a configuration in which the entire memory cell array is divided into a number of unit blocks, many rows of sense amplifiers need to be provided. Therefore, it is a problem that circuit scale increases thereby increasing chip area.